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LTM9002 1 9002f typical application features applications description 14-bit dual-channel if/ baseband receiver subsystem the ltm ? 9002 is a 14-bit dual-channel if receiver sub- system. utilizing an integrated system in a package (sip) technology, it includes a dual high-speed 14-bit a/d con- verter, matching network, anti-aliasing ? lter and two low noise, differential ampli? ers. it is designed for digitizing wide dynamic range signals with an intermediate frequency (if) up to 300mhz. the ampli? ers allow either ac- or dc- coupled input drive. lowpass or bandpass ? lter networks can be implemented with various bandwidths. contact linear technology regarding customization. the LTM9002 is perfect for demanding communications applications, with ac performance that includes 66db snr and 76db spurious free dynamic range (sfdr). auxiliary dacs allow gain balancing between channels. a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.3v logic. an optional multiplexer allows both channels to share a digital output bus. two single-ended clk inputs can be driven together or independently. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. dual channel if receiver n integrated dual 14-bit, high-speed adc, passive filters and fixed gain differential ampli? ers n up to 300mhz if range lowpass and bandpass filter versions n integrated low noise, low distortion ampli? ers fixed gain: 8db, 14db, 20db or 26db 50, 200 or 400 input impedance n integrated bypass capacitance, no external components required n 66db snr up to 140mhz input (LTM9002-aa) n 76db sfdr up to 140mhz input (LTM9002-aa) n auxiliary 12-bit dacs for gain adjustment n clock duty cycle stabilizer n single 3v to 3.3v supply n low power: 1.3w (665mw/ch.) n shutdown and nap modes n 15mm 11.25mm lga package n telecommunications n direct conversion receivers n main and diversity receivers n cellular base stations of gnd lo v cc = 3v v dd differential amplifiers main rf ina C ina + v ref ov dd 0.5v to 3.6v saw filter mux clkout adc clk spi 14-bit 125msps adc 9002 ta01 lo diversity rf inb C inb + ognd saw filter 14-bit 125msps adc dac dac frequency (mhz) amplitude (dbfs) 9002 ta01b 0 C80 C70 C90 C100 C110 C60 C50 C40 C30 C20 C10 C120 0 5 10 15 20 25 30 64k point fft, f in = 15mhz, C1dbfs, sense = v dd , channel a (LTM9002-la) l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
LTM9002 2 9002f pin configuration absolute maximum ratings supply voltage (v cc ) ................................ C0.3v to 3.6v supply voltage (v dd , ov dd ) ......................... C0.3v to 4v digital output ground voltage (ognd) ........ C0.3v to 1v input current (in + , in C ) ........................................10ma dac digital input voltage ( cs /ld, sdi, sck) ................................... C0.3v to 6v digital input voltage (except ampshdn) ................. C0.3v to (v dd + 0.3v) digital input voltage (ampshdn) ..............................C0.3v to (v cc + 0.3v) digital output voltage ................C0.3v to (ov dd + 0.3v) operating temperature range LTM9002c................................................ 0c to 70c LTM9002i ............................................. C40c to 85c storage temperature range ...................C65c to 125c (notes 1, 2) 2 3 4 5 6 7 8 9 10 11 112 a b c d e f g h j lga package 108-lead (15mm 11.25mm 2.32mm) v cc ina + senseb sensea all others = gnd data control clka clkb ina C inb C inb + v dd ov dd ognd ognd ov dd t jmax = 125c, ja = 19c/w, jctop = 16c/w, jcbot = 6c/w ja derived from 101.5mm 114.5mm pcb with 4 layers weight = 0.935g lead free finish tray part marking* package description temperature range LTM9002cv-aa#pbf LTM9002cv-aa#pbf LTM9002vaa 108-lead (15mm 11.25mm 2.3mm) lga 0c to 70c LTM9002cv-la#pbf LTM9002cv-la#pbf LTM9002vla 108-lead (15mm 11.25mm 2.3mm) lga 0c to 70c LTM9002iv-aa#pbf LTM9002iv-aa#pbf LTM9002vaa 108-lead (15mm 11.25mm 2.3mm) lga C40c to 85c LTM9002iv-la#pbf LTM9002iv-la#pbf LTM9002vla 108-lead (15mm 11.25mm 2.3mm) lga C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ order information
LTM9002 3 9002f symbol parameter conditions min typ max units g diff gain dc, LTM9002-aa f in = 140mhz l 25 26 25 27 db db channel a, dc (LTM9002-la) f in = 15mhz channel b, dc (LTM9002-la) f in = 15mhz l l 19.4 7.5 20 19 8 7 20.6 8.5 db db db db g temp gain temperature drift v in = max, (note 3) 1.5 mdb/c gain matching external reference 5 mdb v in input voltage range for C1dbfs both channels, f in = 140mhz (LTM9002-aa) 100 mv p-p channel a, f in = 15mhz (LTM9002-la) 200 mv p-p channel b, f in = 15mhz (LTM9002-la) 800 mv p-p v incm input common mode voltage range 1 1.5 v r indiff differential input impedance both channels (LTM9002-aa) 50 channel a (LTM9002-la) channel b (LTM9002-la) 200 400 c indiff differential input capacitance includes parasitic 1 pf v os offset error (note 5) including ampli? er and adc l C5 0.3 5 mv offset matching 0.3 mv offset drift including ampli? er and adc 10 v/c cmrr common mode rejection ratio 50 db i sense sense input leakage 0v < sense < 1v l C3 3 a i mode mode input leakage 0v < mode < v dd l C3 3 a t ap sample and hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. unless otherwise noted. (note 3) symbol parameter conditions min typ max units adc characteristics resolution (no missing codes) LTM9002-aa l 14 bits LTM9002-la l 12 bits inl integral linearity error (note 4) LTM9002-aa 1.5 lsb LTM9002-la 0.3 lsb dnl differential linearity error LTM9002-aa l C1 0.6 1 lsb LTM9002-la l C1 0.2 1 lsb converter characteristics the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3)
LTM9002 4 9002f symbol parameter conditions min typ max units logic inputs (clk, oe , adcshdn, mux, cs /ld, sck, sdi) v ih high level input voltage v dd = 3v l 2v v il low level input voltage v dd = 3v l 0.8 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 6) 3 pf digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. parameter conditions min typ max units resolution l 12 bits monotonicity l 12 bits full-scale range internal reference 1.5 v settling time 0.024% (1lsb at 12 bits), no external sense capacitor 83.5 s auxiliary dac characteristics the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (not applicable for LTM9002-la) (note 3) dynamic accuracy the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. input = C1dbfs. (note 3) symbol parameter conditions min typ max units snr signal-to-noise ratio 70mhz input (both channels), LTM9002-aa 140mhz input (both channels), LTM9002-aa l 61.5 66 66 dbfs dbfs 15mhz input (channel a), LTM9002-la 15mhz input (channel b), LTM9002-la l l 67.7 68.5 69.9 71.1 dbfs dbfs sfdr spurious free dynamic range, 2nd or 3rd harmonic 70mhz input (both channels), LTM9002-aa 140mhz input (both channels), LTM9002-aa l 67.5 82 76 dbc dbc 15mhz input (channel a), LTM9002-la 15mhz input (channel b), LTM9002-la l l 75 72.7 86.2 85.5 dbc dbc sfdr spurious free dynamic range 4th or higher 70mhz input (both channels), LTM9002-aa 140mhz input (both channels), LTM9002-aa l 74.2 90 90 dbc dbc 15mhz input (channel a), LTM9002-la 15mhz input (channel b), LTM9002-la l l 78.8 79.8 88.5 90.7 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 70mhz input (both channels), LTM9002-aa 140mhz input (both channels), LTM9002-aa l 60.7 66 66 dbfs dbfs 15mhz input (channel a), LTM9002-la 15mhz input (channel b), LTM9002-la l l 67.1 67.9 69.7 70.8 dbfs dbfs imd3 third order inter-modulation distortion; 1mhz tone spacing, two tones C7dbfs 70mhz input, LTM9002-aa 140mhz input, LTM9002-aa 77 73 dbc dbc 15mhz input, LTM9002-la 77 dbc crosstalk 140mhz input, LTM9002-aa C110 db 15mhz input, LTM9002-la C110 db
LTM9002 5 9002f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 7) power requirements symbol parameter conditions min typ max units v cc ampli? er and auxiliary dac operating supply range l 2.85 3.0 3.4 v v dd adc analog supply voltage l 2.85 3.0 3.5 v o vdd output supply voltage l 0.5 3.0 3.6 v i cc ampli? er dac powered up, both ampli? ers enabled, LTM9002-aa l 180 207 ma both ampli? ers enabled, LTM9002-la l 90 120 ma i cc(shdn) ampli? er shutdown supply current ampshdn = 3v, dac powered down 0.7 ma i dd(adc) adc supply current LTM9002-aa l 263 313 ma LTM9002-la l 140 159 ma p d(shdn) adc shutdown power (each channel) adcshdn = ampshdn = 3v, oe = 3v, no clk 2 mw p d(nap) adc nap mode power (each channel) adcshdn = ampshdn = 3v, oe = 0v, no clk 15 mw p d(amp) ampli? er power dissipation dac powered up, LTM9002-aa 540 mw LTM9002-la 270 mw p d(adc) adc power dissipation LTM9002-aa l 790 939 mw LTM9002-la l 420 477 mw p d(total) total power dissipation f sample = max, LTM9002-aa f sample = max, LTM9002-la 1329 690 mw mw digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units logic inputs (ampshdn) v il low level input voltage l 0.8 v v ih high level input voltage l 2.4 v i il input low current ampshdn = 0.8v l 0.5 a i ih input high current ampshdn = 2.4v l 1.4 3 a logic outputs ov dd = 3v c oz hi-z output capacitance oe = 3v (note 6) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a l 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma l 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.1 v
LTM9002 6 9002f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: ov dd = v cc = v dd = 3v, f sample = max, input range = v in with differential drive, clka = clkb, v incm = 1.25v, ampshdn = adcshdn = 0v, unless otherwise noted. symbol parameter conditions min typ max units f s sampling frequency LTM9002-aa l 1 125 mhz LTM9002-la l 1 65 mhz t l clk low time duty cycle stabilizer off (note 6), LTM9002-aa duty cycle stabilizer on (note 6), LTM9002-aa l l 3.8 3 4 4 500 500 ns ns t h clk high time duty cycle stabilizer off (note 6), LTM9002-aa duty cycle stabilizer on (note 6), LTM9002-aa l l 3.8 3 4 4 500 500 ns ns t l clk low time duty cycle stabilizer off (note 6), LTM9002-la duty cycle stabilizer on (note 6), LTM9002-la l l 7.3 5 7.7 7.7 500 500 ns ns t h clk high time duty cycle stabilizer off (note 6), LTM9002-la duty cycle stabilizer on (note 6), LTM9002-la l l 7.3 5 7.7 7.7 500 500 ns ns t ap absolute aperture delay 0ns t d clk to data delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns t c clk to clkout delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns data to clkout skew (t d C t c ) (note 6) l C0.6 0 0.6 ns t md mux to data delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 6) l 4.3 10 ns bus relinquish time (note 6) l 3.3 8.5 ns pipeline latency 5 cycles spi interface for aux dacs, v dd = 2.7v to 3.6v t 1 sdi valid to sck setup 4 ns t 2 sdi valid to sck hold 4 ns t 3 sck high time 9ns t 4 sck low time 9ns t 5 cs /ld pulse width 10 ns t 6 lsb sck high to cs /ld 7 ns t 7 cs /ld low to sck high 7 ns t 10 cs /ld high to sck positive edge 7 ns sck frequency 50% duty cycle 50 mhz the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 6) (not applicable for LTM9002-la) timing characteristics note 4: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 5: offset error is the output code resulting when the inputs are shorted together. the output code is converted to millivolts. note 6: guaranteed by design, not subject to test. note 7: v dd = 3v, f sample = max, input range = v in with differential drive. the supply current and power dissipation are the sum total for both channels with both channels active.
LTM9002 7 9002f t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t c t l n C 4 n C 3 n C 2 n C 1 clka = clkb d0-d13, of 9002 td01 clkout n C 5 n dual digital output bus timing timing diagrams multiplexed digital output bus timing t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a C 5 b C 5 b C 5 a C 5 a C 4 b C 4 b C 4 a C 4 a C 3 b C 3 b C 3 a C 3 a C 2 b C 2 b C 2 a C 2 a C 1 b C 1 a + 2 a + 4 a + 3 a analog input a t h t d t c t md t l clka = clkb = mux da0-da13 9002 td02 clkout db0-db13
LTM9002 8 9002f timing diagrams auxiliary dac timing sdi cs/ld sck 9002 td03 t 2 t 10 t 5 t 7 t 6 t 1 t 3 t 4 1232324 c3 c2 c1 d1 d0 differential non-linearity (dnl) vs output code integral non-linearity (inl), best fit vs output code snr vs frequency input impedance vs frequency if frequency response output code 0 dnl error (lsb) 1.0 0.8 0.4 C0.4 C0.2 0.6 0.2 0 C0.6 C0.8 C1.0 12288 8192 9002 g01 16384 4096 output code 0 inl error (lsb) 4.0 3.0 1.0 C2.0 C1.0 2.0 0 C3.0 C4.0 12288 8192 9002 g02 16384 4096 if frequency (mhz) snr (db) 9002 g03 72 71 63 64 65 66 67 68 69 70 62 1 100 1000 10 frequency (mhz) impedance magnitude () impedance phase (deg) 9002 g04 60 55 15 10 5 20 25 30 35 40 45 50 0 10 magnitude phase 9 1 0 C1 2 3 4 5 6 7 8 C2 1 100 1000 10 if frequency (mhz) amplitude (dbfs) 9002 g05 0 C14 C16 C18 C12 C10 C8 C6 C4 C2 C20 1 100 1000 10 typical performance characteristics (LTM9002-aa)
LTM9002 9 9002f typical performance characteristics 64k point fft, f in = 70mhz, C1dbfs, sense = v dd 64k point 2-tone fft, f in = 70mhz and f in = 74mhz, C7dbfs per tone, sense = v dd 64k point fft, f in = 140mhz, C1dbfs, sense = v dd 64k point 2-tone fft, f in = 136mhz and f in = 140mhz, C7dbfs per tone, sense = v dd (LTM9002-aa) frequency (mhz) amplitude (dbfs) 9002 g06 0 C80 C70 C90 C110 C100 C60 C50 C40 C30 C20 C10 C120 0 2030405060 10 frequency (mhz) amplitude (dbfs) 9002 g07 0 C80 C70 C90 C110 C100 C60 C50 C40 C30 C20 C10 C120 0 2030405060 10 frequency (mhz) amplitude (dbfs) 9002 g08 0 C80 C70 C90 C110 C100 C60 C50 C40 C30 C20 C10 C120 0 2030405060 10 frequency (mhz) amplitude (dbfs) 9002 g09 0 C80 C70 C90 C110 C100 C60 C50 C40 C30 C20 C10 C120 0 2030405060 10 differential non-linearity (dnl) vs output code integral non-linearity (inl), best fit vs output code snr vs frequency (channel a) output code dnl error (lsb) 9002 g10 1.0 C0.6 C0.4 C0.8 C0.2 0 0.2 0.4 0.6 0.8 C1.0 0 1024 2048 3072 4096 output code inl error (lsb) 9002 g11 0.5 C0.3 C0.2 C0.4 C0.1 0 0.1 0.2 0.3 0.4 C0.5 0 1024 2048 3072 4096 if frequency (mhz) snr (db) 9002 g12 72 71 70 69 68 67 66 65 64 63 62 1 10 100 (LTM9002-la)
LTM9002 10 9002f typical performance characteristics input impedance vs frequency (channel b) if frequency response 64k point fft, f in = 15mhz, C1dbfs, sense = v dd (channel a) 64k point fft, f in = 15mhz, C1dbfs, sense = v dd (channel b) (LTM9002-la) frequency (mhz) impedance magnitude () impedance phase (deg) 9002 g15 400 350 50 100 150 200 250 300 0 32 magnitude phase 4 8 12 16 20 24 28 0 1 100 1000 10 if frequency (mhz) amplitude (dbfs) 9002 g16 0 C2 C12 C10 C8 C6 C4 C14 0.1 10 100 1 frequency (mhz) amplitude (dbfs) 9002 g17 0 C80 C70 C90 C100 C100 C60 C50 C40 C30 C20 C10 C120 0 5 10 15 20 25 30 35 frequency (mhz) amplitude (dbfs) 9002 g18 0 C80 C70 C90 C100 C100 C60 C50 C40 C30 C20 C10 C120 0 5 10 15 20 25 30 35 64k point 2-tone fft, f in = z and f in = 15mhz, C7dbfs per tone, sense = v dd (channel a) 64k point 2-tone fft, f in = 14mhz and f in = 15mhz, C7dbfs per tone, sense = v dd (channel b) frequency (mhz) amplitude (dbfs) 9002 g19 0 C80 C70 C90 C100 C100 C60 C50 C40 C30 C20 C10 C120 0 5 10 15 20 25 30 35 frequency (mhz) amplitude (dbfs) 9002 g20 0 C80 C70 C90 C100 C100 C60 C50 C40 C30 C20 C10 C120 0 5 10 15 20 25 30 35 snr vs frequency (channel b) input impedance vs frequency (channel a) if frequency (mhz) snr (db) 9002 g13 72 71 70 69 68 67 66 65 64 63 62 1 10 100 frequency (mhz) impedance magnitude () impedance phase (deg) 9002 g14 200 175 25 50 75 100 125 150 0 8 magnitude phase 1 2 3 4 5 6 7 0 1 100 1000 10
LTM9002 11 9002f pin functions supply pins gnd (pins a1-2, a5-7, b2-4, b6, c2-3, c6, d1-3, d5-7, d9-10, e5-6, e9-10, f1-2, f5-7, f9-10, g2-3, g6, h2-4, h6, j1-2, j5-7): adc power ground. ognd (pins a12, c9, g9, j12): output driver ground. ov dd (pins b12, h12): positive supply for the adc output drivers. the speci? ed operating range is 0.5v to 3.6v. ov dd is internally bypassed to ognd. v cc (pins e3, e4): ampli? er and auxiliary dac power sup- ply. the speci? ed operating range is 2.85v to 3.465v. the voltage on this pin provides power for the ampli? er stage and auxiliary dacs only and is internally bypassed to gnd. note that LTM9002-la does not have auxiliary dacs. v dd (pins e7, e8): analog 3v supply for adc. the speci? ed operating range is 2.7v to 3.6v. v dd is internally bypassed to gnd. analog inputs clka (pin a3): channel a adc clock input. the input sample starts on the positive edge. clkb (pin a4): channel b adc clock input. the input sample starts on the positive edge. dnc1 (pin h5): do not connect. these pins are used for testing and should not be connected on the pcb. they should be soldered to unconnected pads and should be well isolated. the dnc pins connect to the signal path prior to the adc inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. dnc1 connects near the channel a positive differential analog input. dnc2 (pin g5): do not connect. these pins are used for testing and should not be connected on the pcb. they should be soldered to unconnected pads and should be well isolated. the dnc pins connect to the signal path prior to the adc inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. dnc2 connects near the channel a negative differential analog input. dnc3 (pin c5): do not connect. these pins are used for testing and should not be connected on the pcb. they should be soldered to unconnected pads and should be well isolated. the dnc pins connect to the signal path prior to the adc inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. dnc3 connects near the channel b positive differential analog input. dnc4 (pin b5): do not connect. these pins are used for testing and should not be connected on the pcb. they should be soldered to unconnected pads and should be well isolated. the dnc pins connect to the signal path prior to the adc inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. dnc4 connects near the channel b negative differential analog input. dnc5 (pin g4): do not connect. this pin is used for test- ing and should not be connected on the pcb. it should be soldered to an unconnected pad and should be well isolated. this is a test point for the auxiliary dac channel a voltage output. dnc6 (pin c4): do not connect. this pin is used for test- ing and should not be connected on the pcb. it should be soldered to an unconnected pad and should be well isolated. this is a test point for the auxiliary dac channel b voltage output. ina C (pin g1): channel a negative (inverting) ampli? er input. ina + (pin h1): channel a positive (noninverting) am- pli? er input. inb C (pin c1): channel b negative (inverting) ampli? er input. inb + (pin b1): channel b positive (noninverting) am- pli? er input.
LTM9002 12 9002f control pins adcshdna (pin g7): channel a shutdown mode selec- tion pin. connecting adcshdna to gnd and oea to gnd results in normal operation with the outputs enabled. connecting adcshdna to gnd and oea to v dd results in normal operation with the outputs at high impedance. connecting adcshdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting adcshdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance. adcshdnb (pin c7): channel b shutdown mode selec- tion pin. connecting adcshdnb to gnd and oeb to gnd results in normal operation with the outputs enabled. connecting adcshdnb to gnd and oeb to v dd results in normal operation with the outputs at high impedance. connecting adcshdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting adcshdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance. ampshdna (pin e1): power shutdown pin for channel a ampli? er. this pin is a logic input referenced to analog ground. ampshdn = low results in normal operation. ampshdn = high results in powered down ampli? er with a <1ma ampli? er supply current. ampshdnb (pin e2): power shutdown pin for channel b ampli? er. this pin is a logic input referenced to analog ground. ampshdn = low results in normal operation. ampshdn = high results in powered down ampli? er with a <1ma ampli? er supply current. mode (pin g8): output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. mux (pin c8): digital output multiplexer control. if mux = high, channel a comes out on dax; channel b comes out on dbx. if mux = low, the output busses are swapped and channel a comes out on dbx; channel b comes out on dax. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. oea (pin f8): channel a output enable pin. refer to adcshdna pin function. oeb (pin d8): channel b output enable pin. refer to adcshdnb pin function. sensea (pin j4): channel a reference programming pin. connecting sensea to v dd selects the internal reference and the higher input range. connecting to 1.5v selects the lower range. an external reference greater than 0.5v and less than 1v applied to sensea selects an input range of v sensea /gain. see sense pin operation section. senseb (pin j3): channel b reference programming pin. connecting senseb to v dd selects the internal reference and the higher input range. connecting to 1.5v selects the lower range. an external reference greater than 0.5v and less than 1v applied to senseb selects an input range of v senseb /gain. see sense pin operation section. digital inputs (not connected on LTM9002-la) cs /ld (pin f3): serial interface chip select/load input for auxiliary dac. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the speci? ed command (see table 3) is executed. sck (pin f4): serial interface clock input for auxiliary dac. cmos and ttl compatible. sdi (pin d4): serial interface data input for auxiliary dac. data is applied to sdi for transfer to the device at the rising edge of sck. the auxiliary dac accepts input word lengths of either 24 or 32 bits. pin functions
LTM9002 13 9002f pin con? guration (LTM9002-aa) 123456789101112 j gnd gnd senseb sensea gnd gnd gnd da8 da5 da6 da7 ognd h ina + gnd gnd gnd dnc1 gnd of da10 da12 da11 da9 ov dd g ina C gnd gnd dnc5 dnc2 gnd adc shdna mode ognd da13 da4 da3 f gnd gnd cs /ld sck gnd gnd gnd oea gnd gnd da2 da1 e amp shdna amp shdnb v cc v cc gnd gnd v dd v dd gnd gnd da0 clkout d gnd gnd gnd sdi gnd gnd gnd oeb gnd gnd db13 db12 c inb C gnd gnd dnc6 dnc3 gnd adc shdnb mux ognd db1 db11 db10 b inb + gnd gnd gnd dnc4 gnd db0 db4 db2 db3 db5 ov dd a gnd gnd clka clkb gnd gnd gnd db6 db9 db8 db7 ognd pin functions pin con? guration (LTM9002-la) 123456789101112 j gnd gnd senseb sensea gnd gnd gnd da6 da3 da4 da5 ognd h ina + gnd gnd gnd dnc1 gnd ofa da8 da10 da9 da7 ov dd g ina C gnd gnd dnc5 dnc2 gnd adc shdna mode ognd da11 da2 da1 f gnd gnd nc nc gnd gnd gnd oea gnd gnd da0 nc e amp shdna amp shdnb v cc v cc gnd gnd v dd v dd gnd gnd nc ofb d gnd gnd gnd nc gnd gnd gnd oeb gnd gnd db11 db10 c inb C gnd gnd dnc6 dnc3 gnd adc shdnb mux ognd nc db9 db8 b inb + gnd gnd gnd dnc4 gnd nc db2 db0 db1 db3 ov dd a gnd gnd clka clkb gnd gnd gnd db4 db7 db6 db5 ognd digital outputs clkout (pin e12, LTM9002-aa): adc data ready clock output. latch data on the falling edge of clkout. clkout is derived from clkb. tie clka to clkb for simultaneous operation. ofb (pin e12, LTM9002-la): over? ow/under? ow output. high when an over? ow or under? ow has occurred on channel b. da0 C da13 (refer to pin con? guration table): channel a adc digital outputs. da13 is the msb for LTM9002-aa; da11 is the msb for LTM9002-la. db0 C db13 (refer to pin con? guration table): channel b adc digital outputs. db13 is the msb for LTM9002-aa; db11 is the msb for LTM9002-la. of (pin h7, LTM9002-aa): over? ow/under? ow output. high when an over? ow or under? ow has occurred on either channel a or channel b. ofa (pin h7, LTM9002-la): over? ow/under? ow output. high when an over? ow or under? ow has occurred on channel a.
LTM9002 14 9002f block diagram functional block diagram (only one channel is shown) 9001 bd ov dd adc shdn oe mode clk adc driver ref buffer diff ref amp input s/h control logic output drivers differential input low jitter clock driver internal clock signals refh refl sense sdi sck gnd cs /ld d13 d0 of* clkout * ognd filter voltage reference shift register and error correction pipelined adc sections 1st 2nd 3rd 4th 5th 6th v cc in + in C ampshdn voltage reference dac *ofa and ofb on LTM9002-la v dd v dd v cc
LTM9002 15 9002f operation dynamic performance definitions signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen- tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the ? rst ? ve harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + k vn 2 ( ) /v1 where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the ? fth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodula- tion distortion is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. aperture delay time the time from when clk reaches mid supply to the in- stant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal-to-noise ratio due to the jitter alone will be: snrjitter = C20log (2) ? f in ? t jitter crosstalk the amount of signal coupled from one channel into the other. this is measured by applying a full-scale sinusoidal input on channel a, shorting the inputs of channel b and taking the ratio of the signal powers in an fft.
LTM9002 16 9002f figure 1. basic functional elements table 1. semi-custom options amplifier if range amplifier input impedance amplifier gain filter adc sample rate adc resolution auxiliary dac part number 300mhz 50 26db 170mhz lpf 125msps 14-bit 12-bit, spi LTM9002-aa 140mhz 200 (channel a) 400 (channel b) 20db (channel a) 8db (channel b) 25mhz lpf 65msps 12-bit none LTM9002-la select combination of options from columns below dc-300mhz 50 26db tbd 125msps 14-bit 12-bit, i 2 c dc-140mhz 200 20db 105msps 12-bit none dc-70mhz 200 14db 80msps 10-bit dc-35mhz 400 8db 65msps 40msps 25msps 10msps 9002 f01 amplifier adc adc input network auxiliary dac description the LTM9002 is an integrated system in a package (sip) that includes two high-speed 14-bit a/d converters, matching networks, anti-aliasing ? lters and two low noise, differen- tial ampli? ers with ? xed gain. these ampli? ers need not be the same, so that the gains and input impedances of the two channels are different. also included is a pair of auxiliary dacs to allow for digital, full-scale adjustment of each channel. the LTM9002 is designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 300mhz. typical applications include digitizing in-phase and quadrature channels or main and diversity channels in base station applications. the following sections describe in further detail the op- eration of each section. the sip technology allows the LTM9002 to be customized and this is described in the ? rst section. the outline of the remaining sections follows the basic functional elements as shown in figure 1. semi-custom options the module construction affords a new level of ? exibility in application-speci? c standard products. standard adc and ampli? er components can be integrated regardless of their process technology and matched with passive components to a particular application. the LTM9002-aa, as the ? rst example, is con? gured with a dual 14-bit adc sampling at rates up to 125msps. the ampli? er gain is 26db with an input impedance of 50 and an input range of 100mv p-p (C16dbm). the matching network is designed to optimize the interface between the ampli? er output and the adc under these conditions. additionally, there is a 3rd order lowpass ? lter with a cutoff at 170mhz. the auxiliary dacs allow adjustment of the full-scale range with 12-bit resolution. however, other options are possible through linear technologys semi-custom development program. linear technology has in place a program to deliver other speed, resolution, if range, gain and ? lter con? gurations for nearly any speci? ed application. these semi-custom designs are based on existing adcs and ampli? ers with an appropriately modi? ed matching network. the ? nal subsystem is then tested to the exact parameters de? ned for the application. the ? nal result is a fully integrated, accurately tested and optimized solution in the same package. for more details on the semi-custom receiver subsystem program, contact linear technology. operation
LTM9002 17 9002f operation note that not all combinations in table 1 are possible at this time and speci? ed performance may differ signi? cantly from existing values. amplifier operation the ampli? ers used in the LTM9002 are low noise and low distortion fully differential op amps/adc drivers with operation from dc to 2ghz (C3db bandwidth). the ampli- ? ers are composed of fully differential ampli? ers with on chip feedback and output common mode voltage control circuitry. differential gain and input impedance are set by internal resistors in the feedback network. table 2. ampli? er gain and input impedance gain (db) gain (v/v) z in (differential) 8 2.5 400 14 5 200 20 10 200 26 20 50 the ampli? ers are very ? exible in terms of i/o coupling. they can be ac- or dc-coupled at the inputs. due to the internal connection between input and output, users are advised to keep input common mode voltage between 1v and 1.7v for proper operation. if the inputs are ac-coupled, the input common mode voltage is automatically biased close to the adc input common mode voltage and thus no external circuitry is needed for bias. the input signal can be either single-ended or differential with some difference in distortion performance. adc input network the passive network between the ampli? er output stage and the adc input stage provides a 3rd order topology that can be con? gured for bandpass or lowpass response and different cutoff frequencies and bandwidths. LTM9002- aa, for example, implements a lowpass ? lter designed for 170mhz. converter operation as shown in the block diagram, the analog-to-digital con- verter (adc) is a dual cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value six cycles later (see the timing diagram section). the clk inputs are single-ended. the adc has two phases of operation, determined by the state of the clk input pins. each pipelined stage shown in the block diagram contains an adc, a reconstruction dac and an interstage residue ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h dur- ing this high phase of clk. when clk goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ? fth stages, resulting in a ? fth stage residue that is sent to the sixth stage adc for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. auxiliary dac operation the full-scale voltage span of each adc is controlled by an auxiliary voltage output dac connected to sense. series resistance in the dac output allows an external voltage to override the dac. the internal reference sets both auxiliary dacs to a full- scale range to 1.5v. programming the dac to generate an internal voltage greater than or less than the external
LTM9002 18 9002f operation reference adjusts the adc span proportionately; see adjusting the full-scale input range. powering down the auxiliary dac disables the adc span trim control. when the auxiliary dac is powered down, connect sense to v dd or an external reference. power-on reset the auxiliary dacs clear the outputs to zero-scale when power is ? rst applied, making system initialization con- sistent and repeatable. transfer function the digital-to-analog transfer function is; v out(ideal) = ( k/2 n ) v ref where k is the decimal equivalent of the binary dac input code, n is the resolution and v ref is 1.5v, the internal reference voltage of the adc. serial interface all serial interface pins ( cs /ld, sck and sdi) have ttl input levels and are 5v tolerant. the cs /ld input is level trig- gered. when this input is taken low, it acts as a chip-select signal, activating the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded ? rst; then the 4-bit dac address, a3-a0; and ? nally the 16-bit data word. the data word comprises the 12-bit input code, ordered msb-to-lsb, followed by 4 dont-care bits. data can only be transferred to the device when the cs /ld signal is low. the rising edge of cs /ld ends the data transfer and causes the device to carry out the action speci? ed in the 24-bit input word. the complete sequence is shown in figure 3. the command (c3-c0) and address (a3-a0) assignments are shown in table 3. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n . an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24-bits, it may optionally be extended to 32-bits to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). to use the 32-bit word width, 8 dont-care bits are transferred to the device ? rst, followed by the 24-bit word as just described. figure 4 shows the 32-bit sequence. power-down mode either or both dac channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, n . the 16-bit data word is ignored. normal operation can be resumed by executing any com- mand which includes a dac update, as shown in table 3. the selected dac is powered up as its voltage output is updated. if both dacs are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac ampli? ers and reference inputs. in this case, the power-up delay time is 700s (for v cc = 3v). table 3. auxiliary dac commands command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power-up) dac register n 0 0 1 0 write to input register n , update (power up) all n 0 0 1 1 write to and update (power-up) n 0100power down n 1111no o peration address ( n )* a3 a2 a1 a0 0000dac a 0001dac b 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used.
LTM9002 19 9002f operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs/ld sck sdi command word address word data word 24-bit input word 9002 f02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs/ld sck sdi command word address word data word dont care 9002 f03 figure 2. auxiliary dac 24-bit load sequence (minimum input word) figure 3. auxiliary dac 32-bit load sequence
LTM9002 20 9002f figure 4. input termination for differential 50 input impedance using shunt resistor figure 5. input termination for differential 50 input impedance using a balun applications information input span the LTM9002 is con? gured with a given input span and input impedance. with the ampli? er gain and the adc input network described above for LTM9002-aa, the full-scale input range of the driver circuit is 0.1v p-p . the recommended adc input span is achieved by tying the sense pin to v dd . however, the adc input span can be changed if required for the application. the resulting input span at the in + /in C pins is the adc input span divided by the gain. the LTM9002 is intended to be driven through the in + and in C pins. the dnc pins are used for test purposes and are not intended to be used in the application. these are test points within the adc input ? lter network. however, care should be taken with these pins as they connect directly to the internal signal path. they should be soldered to an unconnected pad and should be well isolated. input impedance and matching the input impedance of the ampli? er is 50, 200 or 400 depending on the gain of the ampli? er. in some applications the differential inputs may need to be ter- minated to a lower value impedance, e.g. 50, in order to provide an impedance match for the source. several choices are available. one approach is to use a differential shunt resistor (figure 4). another approach is to employ a wide band transformer and shunt resistor (figure 5). both methods provide a wide band match. the termination resistor or the transformer must be placed close to the input pins in order to minimize the re? ection due to input mismatch. alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction. referring to figure 6, ampli? er inputs can be easily con- ? gured for single-ended input without a balun. the signal is fed to one of the inputs through a matching network while the other input is connected to the same matching network and a source resistor. because the return ratios of the two feedback paths are equal, the two outputs have the same gain and thus symmetrical swing. in general, the single-ended input impedance and termination resis- tor r t are determined by the combination of r s , r g and r f , see table 5. table 4. differential ampli? er input termination values gain (db) z in /2 r t figure 4 r t figure 5 8 200 57 400 14 100 66.5 none 20 100 66.5 none 26 25 none none 9002 f04 z in /2 r t 500 LTM9002 z in /2 25 25 v in 500 in + in C + C 9002 f05 z in /2 500 LTM9002 z in /2 25 25 v in 500 + C 1:4 ? ? in + in C r t table 5. single-ended ampli? er input termination values gain (db) z in /2 r t figure 6 8 200 59 14 100 68.5 20 100 66.5 26 25 150
LTM9002 21 9002f applications information figure 6. input termination for differential 50 input impedance using shunt resistor figure 7. calculate differential gain the ampli? er is unconditionally stable, i.e. differential stability factor kf > 1 and stability measure b1 > 0. how- ever, the overall differential gain is affected by the source impedance in figure 7: av = | v out /v in | = (500/(r s + z in /2) the noise performance of the ampli? er also depends upon the source impedance and termination. for example, an input 1:4 transformer in figure 5 improves the input noise ? gure by adding 6db gain at the inputs. a trade-off between gain and noise is obvious when constant noise ? gure circle and constant gain circle are plotted within the input smith chart, based on which users can choose the optimal source impedance for a given gain and noise requirement. sense pin operation the internal voltage reference can be con? gured for two pin-selectable input ranges of 0.1v (50mv differential) or 0.5v (25mv differential) for LTM9002-aa. tying the sense pin to v dd selects the higher range; tying the sense pin to 1.5v selects the lower range. for other versions of LTM9002, the input span is either 2v p-p divided by the gain or 1v p-p divided by the gain. an external reference can be used by applying its output directly or through a resistive divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. the sense pin is inter- nally bypassed to ground with a 1f ceramic capacitor. input range the input range can be set based on the application. the 0.1v input range (LTM9002-aa) will provide the best snr performance while maintaining excellent sfdr. the lower input range will have slightly better sfdr performance, but the snr will degrade by 5db. see the typical performance characteristics section. adjusting the full-scale input range to trim the full-scale range of one channel to match that of the other channel, ? rst set the desired range for both channels by applying an external reference to sensea and senseb as shown in figure 8. set the dac codes to approximately match the external reference voltage. ap- ply a full-scale voltage to the input of each channel. read the output of both channels and adjust the setting for the dac of one channel until the desired channel matching has been achieved. the adjustment range and step size depends on the resistor values chosen for or the source resistance of the external reference circuit. the external reference is connected to the sense pin which has 10k (1%) series impedance with the internal dac voltage. for the circuit shown in fig- ure 8, the step size is 76v and the code representing 1v is 0xaab (0.666748 decimal). in this example, the sense voltage trim range is from approximately 0.79v to 1.1v including offset and gain errors. therefore, the effective input span can be trimmed from 39.6mv to 55.2mv with a step size of 3.8v. however, it is not recommended to 9002 f06 z in /2 0.1f 0.1f 500 LTM9002 z in /2 r s 50 r s 50 v in 500 + C 0.1f r t r t in + in C 9002 f07 z in /2 r t 500 LTM9002 z in /2 r s /2 r s /2 v in 500 in + in C + C
LTM9002 22 9002f applications information exceed 50mv. the internal 1000pf capacitor provides a corner frequency of 64khz when used with the 2.5k ex- ternal resistor. an additional 0.1f bypass capacitor may be required at the sense pin. the auxiliary dacs can be used without an external ref- erence in applications that are not sensitive to close-in phase noise such as ccd imaging or oversampling of low amplitude signals. without an external reference, the dac step size will be 366v at the sense pin which results in a 18v step for the input span. in this case, the sense pin may be bypassed with 0.1f capacitor. the auxiliary dacs must be subsequently set each time the LTM9002 is powered up. driving the clock inputs the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (figure 9). the noise performance of the adc can depend on the clock signal quality as much as on the analog input. any noise present on the clk signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, ? lter the clk signal to reduce wideband noise and distortion products generated by the source. figure 8. using an external reference ref buffer 10k 1.25v 1v (open circuit, 4k thevenin resistance) 10k 1000pf 2.5k sense range select ref 1.5v reference LTM9002 9002 f08 dac sdi cs /ld sck figure 9. sinusoidal single-ended clk driver clk 50 0.1f 0.1f 4.7f 1k 1k ferrite bead clean supply sinusoidal clock input 9002 f09 nc7svu04 LTM9002
LTM9002 23 9002f applications information figure 10. clk driver using an lvds or pecl to cmos converter figure 11. lvds or pecl clk driver using a transformer it is recommended that clka and clkb are shorted together and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clka and clkb can be driven by two different signals. if this time delay exceeds 1ns, the performance of the part may degrade. clka and clkb should not be driven by asynchronous signals. figure 10 and figure 11 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solution. the nature of the received signals also has a large bear- ing on how much snr degradation will be experienced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full-scale, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 series resistor to act as both a lowpass ? lter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for re? ections. maximum and minimum conversion rates the maximum conversion rate for the LTM9002-aa is 125msps and the LTM9002-la is 65msps. the lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capaci- tors. the speci? ed minimum operating frequency for the LTM9002 is 1msps. clk 5pf to 30pf etc1-1t 0.1f v cm ferrite bead differential clock input 9002 f11 LTM9002 clk 100 0.1f 4.7f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 9002 f10 LTM9002
LTM9002 24 9002f applications information clock duty cycle stabilizer an optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. using the clock duty cycle stabilizer is recommended for most applications. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. digital outputs table 6 shows the relationship between the analog input voltage, the digital data bits, and the over? ow bit. note that of is high when an over? ow or under? ow has occurred on either channel a or channel b. table 6. output codes vs input voltage, 100mv input span in + C in C (sense = v dd )of d13 - d0 (offset binary) d13 - d0 (2s complement) 50mv 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 0.000000v 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C50mv 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 digital output modes figure 12 shows an equivalent circuit for a single output buffer. each buffer is powered by o vdd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters the digital output loading can affect the performance. the digital outputs of the adc should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. for full-speed operation, the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. figure 12. digital output buffer LTM9002 9002 f12 ov dd v dd v dd 0.1f 43 typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe
LTM9002 25 9002f applications information data format using the mode pin, the adc parallel digital output can be selected for offset binary or 2s complement format. note that mode controls both channel a and channel b. connecting mode to gnd or 1/3 v dd selects straight binary output format. connecting mode to 2/3 v dd or v dd selects 2s complement output format. an external resistive divider can be used to set the 1/3 v dd or 2/3 v dd logic values. table 7 shows the logic states for the mode pin. table 7. mode pin function mode pin output format clock duty cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit for LTM9002-aa, when of outputs a logic high the con- verter is either overranged or underranged on channel a or channel b. note that both channels share a common of pin. of is disabled when channel a is in sleep or nap mode. for LTM9002-la, ofa and ofb indicate either condition for the respective channel. output clock the LTM9002-aa has a delayed version of the clkb input available as a digital output, clkout. the falling edge of the clkout pin can be used to latch the digital output data. clkout is disabled when channel b is in sleep or nap mode. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same supply that powers the logic being driven. for example, if the converter drives a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v, independent of v dd . ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe . oe high disables all data outputs including of. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full-speed operation. the output hi-z state is intended for use during test or initialization. channels a and b have independent output enable pins ( oea , oeb .) sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting adcshdn to gnd results in normal operation. connecting adcshdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and the adc typically dissipates 1mw. when exiting sleep mode, it will take 700s to 1ms for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting adcshdn to v dd and oe to gnd results in nap mode and the adc typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent adcshdn pins (adcshdna, adcshdnb.) channel a is controlled by adcshdna and oea , and channel b is controlled by adcshdnb and oeb . the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode. digital output multiplexer the digital outputs of the adc can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on dax; channel b comes out on dbx. if mux is low,
LTM9002 26 9002f applications information the output busses are swapped and channel a comes out on dbx; channel b comes out on dax. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode.) the multiplexed data is available on either data bus C the unused data bus can be disabled with its oe pin. supply sequencing the v cc pin provides the supply to the ampli? er and the auxiliary dac while the v dd pin provides the supply to the adc. the ampli? er, adc and the dac are separate integrated circuits within the LTM9002; however, there are no supply sequencing considerations beyond standard practice. it is recommended that the ampli? er, adc and dac all use the same low noise, 3.0v supply, but v cc may be operated from a different voltage level if desired. both rails can operate from the same 3.0v linear regulator but place a ferrite bead between the v cc and v dd pins. separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. grounding and bypassing the LTM9002 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the LTM9002 has been optimized for a ? ow-through layout so that the interaction between inputs and digital outputs is minimized. a continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. the LTM9002 is internally bypassed with the adc, (v dd ) and ampli? er and dac (v cc ) supplies returning to a common ground (gnd). the digital output supply (ov dd ) is returned to ognd. additional bypass capacitance is optional and may be required if power supply noise is signi? cant. the differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the LTM9002 is transferred through the bottom-side ground pads. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. recommended layout the high integration of the LTM9002 makes the pc board layout very simple and easy. however, to optimize its electri- cal and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. common ground (gnd) and output ground (ognd) are electrically isolated on the LTM9002, but can be connected on the pcb underneath the part to provide a common return path. ? use multiple ground vias. using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers separat- ing analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as pos- sible, using vias to create high-frequency barriers. this will reduce digital feedback that can reduce the signal-to-noise ratio (snr) and dynamic range of the LTM9002. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in application note 100. the LTM9002 employs gold-? nished pads for use with pb-based or tin-based solder paste. it is inherently pb-free and complies with the jedec (e4) standard. the materi- als declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp.
LTM9002 27 9002f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 108 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 2.22 ?2.42 detail b detail b substrate mold cap 0.27 ?0.37 1.95 ?2.05 z 11.25 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 10.16 bsc 1.27 bsc 13.97 bsc 11 10 9 8 7 6 5 4 3 2 package bottom view dia (0.635) pad 1 3 pads see notes 12 1 a b c d e f g h j suggested pcb layout top view 1.270 1.270 0.000 2.540 2.540 3.810 3.810 5.080 5.080 6.985 6.985 5.715 5.715 4.445 4.445 3.175 3.175 1.905 1.905 0.635 0.635 0.000 lga 108 0707 rev package in tray loading orientation ltmxxxxxx module tray pin 1 bevel component pin ?1 // bbb z 0.22 45 chamfer detail a 0.630 0.025 sq. 108x s y x eee lga package 108-lead (15mm 11.25mm 2.32mm) (reference ltc dwg # 05-08-1757 rev ?)
LTM9002 28 9002f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0509 ? printed in usa related parts part number description comments lt1994 low noise, low distortion fully differential input/ output ampli? er/driver low distortion: C94dbc at 1mhz ltc2205 16-bit, 65msps adc 530mw, 79db snr, 100db sfdr ltc2206 16-bit, 80msps adc 725mw, 77.9db snr, 100db sfdr ltc2207 16-bit, 105msps adc 900mw, 77.9db snr, 100db sfdr ltc2208 16-bit, 130msps adc 1250mw, 77.7db snr, 100db sfdr ltc2240-12 12-bit, 170msps, 2.5v adc, lvds outputs 445mw, 65.6db snr, 80db sfdr, 64-pin qfn ltc2241-12 12-bit, 210msps, 2.5v adc, lvds outputs 585mw, 65.6db snr, 80db sfdr, 64-pin qfn ltc2242-12 12-bit, 250msps, 2.5v adc, lvds outputs 745mw, 65.6db snr, 80db sfdr, 64-pin qfn ltc2248 14-bit, 65msps adc 210mw, 74db snr, 5mm 5mm qfn ltc2249 14-bit, 80msps adc 230mw, 73db snr, 5mm 5mm qfn ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 88db sfdr, 5mm 5mm qfn ltc2255 14-bit, 125msps adc 395mw, 72.4db snr, 88db sfdr, 5mm 5mm qfn ltc2282 dual 12-bit, 105msps adc 540mw, 70.1db snr, 88db sfdr, 64-pin qfn ltc2283 dual 12-bit, 125msps adc 790mw, 70.2db snr, 88db sfdr, 64-pin qfn ltc2284 dual 14-bit, 105msps adc 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2285 dual 14-bit, 125msps adc 790mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2293 dual 12-bit, 65msps adc 410mw, 71db snr, 9mm 9mm qfn ltc2294 dual 12-bit, 80msps adc 445mw, 70.6db snr, 9mm 9mm qfn ltc2295 dual 14-bit, 10msps adc 120mw, 74.4db snr, 9mm 9mm qfn ltc2296 dual 14-bit, 25msps adc 150mw, 74db snr, 9mm 9mm qfn ltc2297 dual 14-bit, 40msps adc 240mw, 74db snr, 9mm 9mm qfn ltc2298 dual 14-bit, 65msps adc 410mw, 74db snr, 9mm 9mm qfn ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm 9mm qfn lt5557 400mhz to 3.8ghz 3.3v high linearity downconverting rf mixer 24.7dbm iip3 at 1.9ghz, nf = 11.7db, single-ended rf and lo ports, 3.3v supply lt5575 800mhz to 2.7ghz high linearity direct conversion quadrature demodulator 60dbm iip2 at 1.9ghz, nf = 12.7db, low dc offsets ltc6400-8/ltc6400-14/ ltc6400-20/ltc6400-26 low noise, low distortion differential ampli? er for 300mhz if, fixed gain of 8db, 14db, 20db or 26db 3v, 90ma, 39.5dbm oip3 at 300mhz, 6db nf ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 low noise, low distortion differential ampli? er for 140mhz if, fixed gain of 8db, 14db, 20db or 26db 3v, 45ma, 45.5dbm oip3 at 140mhz, 6db nf

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